Systems, methods, and apparatuses for dot product operations

ABSTRACT

Embodiments detailed herein relate to matrix operations. For example, embodiments of instruction support for matrix (tile) dot product operations are detailed. Exemplary instructions including computing a dot product of signed words and accumulating in a quadword data elements of a matrix pair. Additionally, in some instances, non-accumulating quadword data elements of the matrix pair are set to zero.

FIELD OF INVENTION

The field of invention relates generally to computer processor architecture, and, more specifically, to matrix manipulation.

BACKGROUND

Matrices are increasingly important in many computing tasks such as machine learning and other bulk data processing.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

FIGS. 1A and 1B illustrate an embodiment of configured tiles;

FIG. 2 illustrates several examples of matrix storage;

FIG. 3 illustrates an embodiment of a system utilizing a matrix (tile) operations accelerator;

FIGS. 4 and 5 show different embodiments of how memory is shared using a matrix operations accelerator;

FIG. 6 illustrates an embodiment of matrix multiply accumulate operation using tiles (“TMMA”);

FIG. 7 illustrates an embodiment of a subset of the execution of an iteration of a chained fused multiply accumulate instruction;

FIG. 8 illustrates an embodiment of a subset of the execution of an iteration of a chained fused multiply accumulate instruction;

FIG. 9 illustrates an embodiment of a subset of the execution of an iteration of a chained fused multiply accumulate instruction;

FIG. 10 illustrates an embodiment of a subset of the execution of an iteration of chained fused multiply accumulate instruction;

FIG. 11 illustrates power-of-two sized SIMD implementations wherein the accumulators use input sizes that are larger than the inputs to the multipliers according to an embodiment;

FIG. 12 illustrates an embodiment of a system utilizing matrix operations circuitry;

FIG. 13 illustrates an embodiment of a processor core pipeline supporting matrix operations using tiles;

FIG. 14 illustrates an embodiment of a processor core pipeline supporting matrix operations using tiles;

FIG. 15 illustrates an example of a matrix expressed in row major format and column major format;

FIG. 16 illustrates an example of usage of matrices (tiles);

FIG. 17 illustrates an embodiment a method of usage of matrices (tiles);

FIG. 18 illustrates support for configuration of the usage of tiles according to an embodiment;

FIG. 19 illustrates an embodiment of a description of the matrices (tiles) to be supported;

FIGS. 20(A)-(D) illustrate examples of register(s);

FIG. 21 illustrates an exemplary execution of a TDPPAIR instruction;

FIG. 22 illustrates an embodiment of method performed by a processor to process a matrix (tile) dot product instruction;

FIG. 23 illustrates additional detailed related to an example method performed by a processor to execute a TDPPAIR instruction, where the instruction has fields for a first source matrix (tile) operand, a second source matrix (tile) operand, and a destination matrix pair (tile pair) operand according to an embodiment;

FIG. 24 illustrates an example of methods for performing tile dot products operations, as described above, according to an embodiment;

FIG. 25A illustrates an exemplary instruction format;

FIG. 25B illustrates which fields from FIG. 25A make up a full opcode field and a base operation field;

FIG. 25C illustrates which fields from FIG. 25A make up a register index field;

FIG. 26 is a block diagram of a register architecture according to one embodiment of the invention;

FIG. 27A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention;

FIG. 27B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention;

FIG. 28A-B illustrate a block diagram of a more specific exemplary in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and/or different types) in a chip;

FIG. 29 is a block diagram of a processor that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention;

FIGS. 30-33 are block diagrams of exemplary computer architectures; and

FIG. 34 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

In many mainstream processors, handling matrices is a difficult and/or instruction intensive task. For example, rows of a matrix could be put into a plurality of packed data (e.g., SIMD or vector) registers and then operated on individually. For example, an add two 8×2 matrices may require a load or gather into four packed data registers depending upon data sizes. Then a first add of packed data registers corresponding to a first row from each matrix is performed and a second add of packed data registers corresponding to a second row from each matrix is performed. Then the resulting packed data registers are scattered back to memory. While for small matrices this scenario may be acceptable, it is often not acceptable with larger matrices.

I. High-Level Discussion

Described herein are mechanisms to support matrix operations in computer hardware such as central processing units (CPUs), graphic processing units (GPUs), and accelerators. The matrix operations utilize 2-dimensional (2-D) data structures representing one or more packed regions of memory such as registers. Throughout this description, these 2-D data structures are referred to as tiles. Note that a matrix may be smaller than a tile (use less than all of a tile), or utilize a plurality of tiles (the matrix is larger than the size of any one tile). Throughout the description, matrix (tile) language is used to indicate operations performed using tiles that impact a matrix; whether or not that matrix is larger than any one tile is not typically relevant.

Each tile may be acted upon by different operations such as those that are detailed herein and include, but are not limited to: matrix (tile) multiplication, tile add, tile subtract, tile diagonal, tile zero, tile transpose, tile dot product, tile broadcast, tile row broadcast, tile column broadcast, tile multiplication, tile multiplication and accumulation, tile move, etc. Additionally, support for operators such as the use of a scale and/or bias may be used with these operations or in support of non-numeric applications in the future, for instance, OpenCL “local memory,” data compression/decompression, etc.

Portions of storage (such as memory (non-volatile and volatile), registers, cache, etc.) are arranged into tiles of different horizontal and vertical dimensions. For example, a tile may have horizontal dimension of 4 (e.g., four rows of a matrix) and a vertical dimension of 8 (e.g., 8 columns of the matrix). Typically, the horizontal dimension is related element sizes (e.g., 2-, 4-, 8-, 16-, 32-, 64-, 128-bit, etc.). Multiple datatypes (single precision floating point, double precision floating point, integer, etc.) may be supported.

A. Exemplary Usage of Configured Tiles

In some embodiments, tile parameters can be configured. For example, a given tile may be configured to provide tile options. Exemplary tile options include, but are not limited to: a number of rows of the tile, a number of columns of the tile, whether the tile is VALID, and whether the tile consists of a pair of equal-sized tiles. In some embodiments, a pair of tiles comprises a first tile being a first half of the columns of a matrix and a second tile being a second half of the columns of the matrix, wherein the columns of the matrix are consecutive columns of each tile. In some embodiments, a pair of tiles comprises a first tile being a first half of the rows of a matrix and a second tile being a second half of the rows of the matrix, wherein the columns of the matrix are consecutive rows of each tile. In some embodiments, a pair of tiles comprises a first tile being a first half of the columns of a matrix and a second tile being a second half of the columns of the matrix, wherein the columns of the matrix are interleaved columns of each tile. In some embodiments, a pair of tiles comprises a first tile being a first half of the rows of a matrix and a second tile being a second half of the rows of the matrix, wherein the columns of the matrix are interleaved rows of each tile.

FIG. 1A illustrates an embodiment of configured tiles. As shown, 4 kB of application memory 102 have stored thereon 4 1 kB tiles, tile 0 104, tile 1 106, tile 2 108, and tile 3 110. In this example, the 4 tiles do not consist of pairs, and each have elements arranged in rows and columns. Tile t0 104 and tile t1 106 have K rows and N columns of 4-byte elements (e.g., single precision data), where K equals 8 and N=32. Tile t2 108 and tile t3 110 have K rows and N/2 columns of 8-byte elements (e.g., double precision data). As the double precision operands are twice the width of single precision, this configuration is consistent with a palette, used to provide tile options, supplying at least 4 names with total storage of at least 4 kB. In operation, the tiles can be loaded from and stored to memory using load and store operations. Depending upon the instruction encoding scheme used, the amount of available application memory, as well as the size, number, and configuration of available tiles varies.

FIG. 1B illustrates an embodiment of configured tiles. As shown, 4 kB of application memory 122 have stored thereon 2 pairs of 1 kB-tiles, the first pair being tile t4L 124 and tile t4R 126, and the second pair being tile t5L 128 and tile t5R 130. As shown the pairs of tiles are divided into a left tile and a right tile. In other embodiments, the pair of tiles are divided into an even tile and an odd tile. In this example, the 4 tiles each have elements arranged in rows and columns. Tile t4L 124 and tile t4R 126 have K rows and N columns of 4-byte elements (e.g., single precision data), where K equals 8 and N equals 32. Tile t5L 128 and tile t5R 130 have K rows and N/2 columns of 8-byte elements (e.g., double precision data). As the double precision operands are twice the width of single precision, this configuration is consistent with a palette, used to provide tile options, supplying at least 2 names with total storage of at least 4 kB. The four tiles of FIG. 1A use 4 names, each naming a 1 kB tile, whereas the 2 pairs of tiles in FIG. 1B can use 2 names to specify the paired tiles. In some embodiments, tile instructions accept a name of a paired tile as an operand. In operation, the tiles can be loaded from and stored to memory using load and store operations. Depending upon the instruction encoding scheme used, the amount of available application memory, as well as the size, number, and configuration of available tiles varies.

In some embodiments, tile parameters are definable. For example, a “palette” is used to provide tile options. Exemplary options include, but are not limited to: the number of tile names, the number of bytes in a row of storage, the number of rows and columns in a tile, etc. For example, a maximum “height” (number of rows) of a tile may be defined as:

Tile Max Rows=Architected Storage/(The Number of Palette Names*The Number of Bytes per row)

As such, an application can be written such that a fixed usage of names will be able to take advantage of different storage sizes across implementations.

Configuration of tiles is done using a tile configuration (“TILECONFIG”) instruction, where a particular tile usage is defined in a selected palette. This declaration includes the number of tile names to be used, the requested number of rows and columns per name (tile), and, in some embodiments, the requested datatype of each tile. In some embodiments, consistency checks are performed during the execution of a TILECONFIG instruction to determine that it matches the restrictions of the palette entry.

B. Exemplary Tile Storage Types

FIG. 2 illustrates several examples of matrix storage. In (A), a tile is stored in memory. As shown, each “row” consists of four packed data elements. To get to the next “row,” a stride value is used. Note that rows may be consecutively stored in memory. Strided memory accesses allows for access of one row to then next when the tile storage does not map the underlying memory array row width.

Tile loads from memory and stores to memory are typically strided accesses from the application memory to packed rows of data. Exemplary TILELOAD and TILESTORE instructions, or other instruction references to application memory as a TILE operand in load-op instructions, are, in some embodiments, restartable to handle (up to) 2*rows of page faults, unmasked floating point exceptions, and/or interrupts per instruction.

In (B), a matrix is stored in a tile comprised of a plurality of registers such as packed data registers (single instruction, multiple data (SIMD) or vector registers). In this example, the tile is overlaid on three physical registers. Typically, consecutive registers are used, however, this need not be the case.

In (C), a matrix is stored in a tile in non-register storage accessible to a fused multiple accumulate (FMA) circuit used in tile operations. This storage may be inside of a FMA, or adjacent to it. Additionally, in some embodiments, discussed below, the storage may be for a data element and not an entire row or tile.

The supported parameters for the TMMA architecture are reported via CPUID. In some embodiments, the list of information includes a maximum height and a maximum SIMD dimension. Configuring the TMMA architecture requires specifying the dimensions for each tile, the element size for each tile and the palette identifier. This configuration is done by executing the TILECONFIG instruction.

Successful execution of a TILECONFIG instruction enables subsequent TILE operators. A TILERELEASEALL instruction clears the tile configuration and disables the TILE operations (until the next TILECONFIG instructions executes). In some embodiments, XSAVE, XSTORE, etc. are used in context switching using tiles. In some embodiments, 2 XCRO bits are used in XSAVE, one for TILECONFIF metadata and one bit corresponding to actual tile payload data.

TILECONFIG not only configures the tile usage, but also sets a state variable indicating that the program is in a region of code with tiles configured. An implementation may enumerate restrictions on other instructions that can be used with a tile region such as no usage of an existing register set, etc.

Exiting a tile region is typically done with the TILERELEASEALL instruction. It takes no parameters and swiftly invalidates all tiles (indicating that the data no longer needs any saving or restoring) and clears the internal state corresponding to being in a tile region.

In some embodiments, tile operations will zero any rows and any columns beyond the dimensions specified by the tile configuration. For example, tile operations will zero the data beyond the configured number of columns (factoring in the size of the elements) as each row is written. For example, with 64-byte rows and a tile configured with 10 rows and 12 columns, an operation writing FP32 elements would write each of the first 10 rows with 12*4 bytes with output/result data and zero the remaining 4*4 bytes in each row. Tile operations also fully zero any rows after the first 10 configured rows. When using 1K tile with 64-byte rows, there would be 16 rows, so in this example, the last 6 rows would also be zeroed.

In some embodiments, a context restore (e.g., XRSTOR), when loading data, enforces that the data beyond the configured rows for a tile will be maintained as zero. If there is no valid configuration, all rows are zeroed. XRSTOR of tile data can load garbage in the columns beyond those configured. It should not be possible for XRSTOR to clear beyond the number of columns configured because there is not an element width associated with the tile configuration.

Context save (e.g., XSAVE) exposes the entire TILE storage area when writing it to memory. If XRSTOR loaded garbage data in to the rightmost part of a tile, that data will be saved by XSAVE. XSAVE will write zeros for rows beyond the number specified for each tile.

In some embodiments, tile instructions are restartable. The operations that access memory allow restart after page faults. The computational instructions that deal with floating point operations also allow for unmasked floating point exceptions, with the masking of the exceptions controlled by a control and/or status register.

To support restarting instructions after events that causes a matrix (tile) operation to break during execution, the instructions store information in the start registers detailed below.

II. Matrix (Tile) Operation Systems

A. Exemplary Hardware Support

FIG. 3 illustrates an embodiment of a system utilizing a matrix (tile) operations accelerator. In this illustration, a host processor/processing system 301 communicates commands 311 (e.g., matrix manipulation operations such as arithmetic or matrix manipulation operations, or load and store operations) to a matrix operations accelerator 307. However, this is shown this way for discussion purposes only. As detailed later, this accelerator 307 may be a part of a processing core. Typically, commands 311 that are tile manipulation operator instructions will refer to tiles as register-register (“reg-reg”) or register-memory (“reg-mem”) format. Other commands such as TILESTORE, TILELOAD, TILECONFIG, etc., do not perform data operations on a tile. Commands may be decoded instructions (e.g., micro-ops) or macro-instructions for the accelerator 307 to handle.

In this example, a coherent memory interface 303 is coupled to the host processor/processing system 301 and matrix operations accelerator 405 such that they can share memory. FIGS. 4 and 5 show different embodiments of how memory is shared using a matrix operations accelerator. As shown in FIG. 4, the host processor 401 and matrix operations accelerator circuitry 405 share the same memory 403. FIG. 5 illustrates an embodiment where the host processor 501 and matrix operations accelerator 505 do not share memory, but can access each other's memory. For example, processor 501 can access tile memory 507 and utilize its host memory 503 as normal. Similarly, the matrix operations accelerator 505 can access host memory 503, but more typically uses its own memory 507. Note these memories may be of different types.

In some embodiments, the matrix operations accelerator 307 includes a plurality of FMAs 309 coupled to data buffers 305 (in some implementations, one or more of these buffers 305 are stored in the FMAs of the grid as shown). The data buffers 305 buffer tiles loaded from memory and/or tiles to be stored to memory (e.g., using a tileload or tilestore instruction). Data buffers may be, for example, a plurality of registers. Typically, these FMAs are arranged as a grid of chained FMAs 309 which are able to read and write tiles. In this example, the matrix operations accelerator 307 is to perform a matrix multiply operation using tiles T0, T1, and T2. At least one of tiles is housed in the FMA grid 309. In some embodiments, all tiles in an operation are stored in the FMA grid 309. In other embodiments, only a subset are stored in the FMA grid 309. As shown, T1 is housed and T0 and T2 are not. Note that A, B, and C refer to the matrices of these tiles which may or may not take up the entire space of the tile.

FIG. 6 illustrates an embodiment of matrix multiply accumulate operation using tiles (“TMMA”).

The number of rows in the matrix (TILE A 601) matches the number of serial (chained) FMAs comprising the computation's latency. An implementation is free to recirculate on a grid of smaller height, but the computation remains the same.

The source/destination vector comes from a tile of N rows (TILE C 605) and the grid of FMAs 611 performs N vector-matrix operations resulting in a complete instruction performing a matrix multiplication of tiles. Tile B 603 is the other vector source and supplies “broadcast” terms to the FMAs in each stage.

In operation, in some embodiments, the elements of matrix B (stored in a tile B 603) are spread across the rectangular grid of FMAs. Matrix B (stored in tile A 601) has its elements of a row transposed to match up with the columnar dimension of the rectangular grid of FMAs. At each FMA in the grid, an element of A and B are multiplied and added to the incoming summand (from above) and the outgoing sum is passed to the next row of FMAs (or the final output).

The latency of a single step is proportional to K (row height of matrix B) and dependent TMMAs typically have enough source-destination rows (either in a single tile or across tile) to hide that latency. An implementation may also split the SIMD (packed data element) dimension M (row height of matrix A) across time steps, but this simply changes the constant that K is multiplied by. When a program specifies a smaller K than the maximum enumerated by the TMACC, an implementation is free to implement this with “masking” or “early outs.”

The latency of an entire TMMA is proportional to N*K. The repeat rate is proportional to N. The number of MACs per TMMA instruction is N*K*M.

FIG. 7 illustrates an embodiment of a subset of the execution of an iteration of a chained fused multiply accumulate instruction. In particular, this illustrates execution circuitry of an iteration of one packed data element position of the destination. In this embodiment, the chained fused multiply accumulate is operating on signed sources wherein the accumulator is 2× the input data size.

A first signed source (source 1 701) and a second signed source (source 2 703) each have four packed data elements. Each of these packed data elements stores signed data such as floating point data. A third signed source (source 3 709) has two packed data elements, each of which stores signed data. The sizes of the first and second signed sources 701 and 703 are half that of the third signed source (initial value or previous result) 709. For example, the first and second signed sources 701 and 703 could have 32-bit packed data elements (e.g., single precision floating point) while the third signed source 709 could have 64-bit packed data elements (e.g., double precision floating point).

In this illustration, only the two most significant packed data element positions of the first and second signed sources 701 and 703 and the most significant packed data element position of the third signed source 709 are shown. Of course, the other packed data element positions would also be processed.

As illustrated, packed data elements are processed in pairs. For example, the data of the most significant packed data element positions of the first and second signed sources 701 and 703 are multiplied using a multiplier circuit 705, and the data from second most significant packed data element positions of the first and second signed sources 701 and 703 are multiplied using a multiplier circuit 707. In some embodiments, these multiplier circuits 705 and 707 are reused for other packed data elements positions. In other embodiments, additional multiplier circuits are used so that the packed data elements are processed in parallel. In some contexts, parallel execution is done using lanes that are the size of the signed third source 709. The results of each of the multiplications are added using addition circuitry 711.

The result of the addition of the results of the multiplications is added to the data from most significant packed data element position of the signed source 3 709 (using a different adder 713 or the same adder 711).

Finally, the result of the second addition is either stored into the signed destination 715 in a packed data element position that corresponds to the packed data element position used from the signed third source 709, or passed on to the next iteration, if there is one. In some embodiments, a writemask is applied to this storage such that if a corresponding writemask (bit) is set, the storage happens, and, if not set, the storage does not happen.

FIG. 8 illustrates an embodiment of a subset of the execution of an iteration of a chained fused multiply accumulate instruction. In particular, this illustrates execution circuitry of an iteration of one packed data element position of the destination. In this embodiment, the chained fused multiply accumulate is operating on signed sources wherein the accumulator is 2× the input data size.

A first signed source (source 1 801) and a second signed source (source 2 803) each have four packed data elements. Each of these packed data elements stores signed data such as integer data. A third signed source (source 3 809) has two packed data elements, each of which stores signed data. The sizes of the first and second signed sources 801 and 803 are half that of the third signed source 809. For example, the first and second signed sources 801 and 803 could have 32-bit packed data elements (e.g., single precision floating point) the third signed source 809 could have 64-bit packed data elements (e.g., double precision floating point).

In this illustration, only the two most significant packed data element positions of the first and second signed sources 801 and 803 and the most significant packed data element position of the third signed source 809 are shown. Of course, the other packed data element positions would also be processed.

As illustrated, packed data elements are processed in pairs. For example, the data of the most significant packed data element positions of the first and second signed sources 801 and 803 are multiplied using a multiplier circuit 805, and the data from second most significant packed data element positions of the first and second signed sources 801 and 803 are multiplied using a multiplier circuit 807. In some embodiments, these multiplier circuits 805 and 807 are reused for other packed data elements positions. In other embodiments, additional multiplier circuits are used so that the packed data elements are processed in parallel. In some contexts, parallel execution is done using lanes that are the size of the signed third source (initial value or previous iteration result) 809. The results of each of the multiplications are added to the signed third source 809 using addition/saturation circuitry 813.

Addition/saturation (accumulator) circuitry 813 preserves a sign of an operand when the addition results in a value that is too big. In particular, saturation evaluation occurs on the infinite precision result between the multi-way-add and the write to the destination or next iteration. When the accumulator 813 is floating point and the input terms are integer, the sum of products and the floating point accumulator input value are turned into infinite precision values (fixed point numbers of hundreds of bits), the addition of the multiplication results and the third input is performed, and a single rounding to the actual accumulator type is performed.

Unsigned saturation means the output values are limited to a maximum unsigned number for that element width (all 1s). Signed saturation means a value is limited to the be in the range between a minimum negative number and a max positive number for that element width (for bytes for example, the range is from −128 (=−2̂7) to 127(=2̂7−1)).

The result of the addition and saturation check is stored into the signed result 815 in a packed data element position that corresponds to the packed data element position used from the signed third source 809, or passed on to the next iteration if there is one. In some embodiments, a writemask is applied to this storage such that if a corresponding writemask (bit) is set, the storage happens, and, if not set, the storage does not happen.

FIG. 9 illustrates an embodiment of a subset of the execution of an iteration of a chained fused multiply accumulate instruction. In particular, this illustrates execution circuitry of an iteration of one packed data element position of the destination. In this embodiment, the chained fused multiply accumulate is operating on a signed source and an unsigned source wherein the accumulator is 4× the input data size.

A first signed source (source 1 901) and a second unsigned source (source 2 903) each have four packed data elements. Each of these packed data elements has data such as floating point or integer data. A third signed source (initial value or result 915) has a packed data element of which stores signed data. The sizes of the first and second sources 901 and 903 are a quarter of the third signed source 915. For example, the first and second sources 901 and 903 could have 16-bit packed data elements (e.g., word) and the third signed source 915 could have 64-bit packed data elements (e.g., double precision floating point or 64-bit integer).

In this illustration, the four most significant packed data element positions of the first and second sources 901 and 903 and the most significant packed data element position of the third signed source 915 are shown. Of course, other packed data element positions would also be processed if there are any.

As illustrated, packed data elements are processed in quadruplets. For example, the data of the most significant packed data element positions of the first and second sources 901 and 903 are multiplied using a multiplier circuit 907, data from second most significant packed data element positions of the first and second sources 901 and 903 are multiplied using a multiplier circuit 907, data from third most significant packed data element positions of the first and second sources 901 and 903 are multiplied using a multiplier circuit 909, and data from the least significant packed data element positions of the first and second sources 901 and 903 are multiplied using a multiplier circuit 911. In some embodiments, the signed packed data elements of the first source 901 are sign extended and the unsigned packed data elements of the second source 903 are zero extended prior to the multiplications.

In some embodiments, these multiplier circuits 905-911 are reused for other packed data elements positions. In other embodiments, additional multiplier circuits are used so that the packed data elements are processed in parallel. In some contexts, parallel execution is done using lanes that are the size of the signed third source 915. The results of each of the multiplications are added using addition circuitry 911.

The result of the addition of the results of the multiplications is added to the data from most significant packed data element position of the signed source 3 915 (using a different adder 913 or the same adder 911).

Finally, the result 919 of the second addition is either stored into the signed destination in a packed data element position that corresponds to the packed data element position used from the signed third source 915, or passed to the next iteration. In some embodiments, a writemask is applied to this storage such that if a corresponding writemask (bit) is set, the storage happens, and, if not set, the storage does not happen.

FIG. 10 illustrates an embodiment of a subset of the execution of an iteration of chained fused multiply accumulate instruction. In particular, this illustrates execution circuitry of an iteration of one packed data element position of the destination. In this embodiment, the chained fused multiply accumulate is operating on a signed source and an unsigned source wherein the accumulator is 4× the input data size.

A first signed source (source 1 1001) and a second unsigned source (source 2 1003) each have four packed data elements. Each of these packed data elements stores data such as floating point or integer data. A third signed source (initial or previous result 1015) has a packed data element of which stores signed data. The sizes of the first and second sources 1001 and 1003 are a quarter of the third signed source 1015. For example, the first and second sources 1001 and 1003 could have 16-bit packed data elements (e.g., word) and the third signed source 1015 could have 64-bit packed data elements (e.g., double precision floating point or 64-bit integer).

In this illustration, the four most significant packed data element positions of the first and second sources 1001 and 1003 and the most significant packed data element position of the third signed source 1015 are shown. Of course, other packed data element positions would also be processed if there are any.

As illustrated, packed data elements are processed in quadruplets. For example, the data of the most significant packed data element positions of the first and second sources 1001 and 1003 are multiplied using a multiplier circuit 1007, data from second most significant packed data element positions of the first and second sources 1001 and 1003 are multiplied using a multiplier circuit 1007, data from third most significant packed data element positions of the first and second sources 1001 and 1003 are multiplied using a multiplier circuit 1009, and data from the least significant packed data element positions of the first and second sources 1001 and 1003 are multiplied using a multiplier circuit 1011. In some embodiments, the signed packed data elements of the first source 1001 are sign extended and the unsigned packed data elements of the second source 1003 are zero extended prior to the multiplications.

In some embodiments, these multiplier circuits 1005-1011 are reused for other packed data elements positions. In other embodiments, additional multiplier circuits are used so that the packed data elements are processed in parallel. In some contexts, parallel execution is done using lanes that are the size of the signed third source 1015. The result of the addition of the results of the multiplications is added to the data from most significant packed data element position of the signed source 3 1015 using addition/saturation circuitry 1013.

Addition/saturation (accumulator) circuitry 1013 preserves a sign of an operand when the addition results in a value that is too big or too small for signed saturation. In particular, saturation evaluation occurs on the infinite precision result between the multi-way-add and the write to the destination. When the accumulator 1013 is floating point and the input terms are integer, the sum of products and the floating point accumulator input value are turned into infinite precision values (fixed point numbers of hundreds of bits), the addition of the multiplication results and the third input is performed, and a single rounding to the actual accumulator type is performed.

The result 1019 of the addition and saturation check is stored into the signed destination in a packed data element position that corresponds to the packed data element position used from the signed third source 1015, or passed to the next iteration. In some embodiments, a writemask is applied to this storage such that if a corresponding writemask (bit) is set, the storage happens, and, if not set, the storage does not happen.

FIG. 11 illustrates power-of-two sized SIMD implementations wherein the accumulators use input sizes that are larger than the inputs to the multipliers according to an embodiment. Note the source (to the multipliers) and accumulator values may be signed or unsigned values. For an accumulator having 2× input sizes (in other words, the accumulator input value is twice the size of the packed data element sizes of the sources), table 1101 illustrates different configurations. For byte sized sources, the accumulator uses word or half-precision floating-point (HPFP) values that are 16-bit in size. For word sized sources, the accumulator uses 32-bit integer or single-precision floating-point (SPFP) values that are 32-bit in size. For SPFP or 32-bit integer sized sources, the accumulator uses 64-integer or double-precision floating-point (DPFP) values that are 64-bit in size.

For an accumulator having 4× input sizes (in other words, the accumulator input value is four times the size of the packed data element sizes of the sources), table 1103 illustrates different configurations. For byte sized sources, the accumulator uses 32-bit integer or single-precision floating-point (SPFP) values that are 32-bit in size. For word sized sources, the accumulator uses 64-bit integer or double-precision floating-point (DPFP) values that are 64-bit in size in some embodiments.

For an accumulator having 8× input sizes (in other words, the accumulator input value is eight times the size of the packed data element sizes of the sources), table 1105 illustrates a configuration. For byte sized sources, the accumulator uses 64-bit integer.

As hinted at earlier, matrix operations circuitry may be included in a core, or as an external accelerator. FIG. 12 illustrates an embodiment of a system utilizing matrix operations circuitry. In this illustration, a plurality of entities are coupled with a ring interconnect 1245.

A plurality of cores 1201, 1203, 1205, and 1207 provide non-tile based instruction support. In some embodiments, matrix operations circuitry is provided in a core 1203, and in other embodiments matrix operations circuitry 1211 and 1213 is accessible on the ring interconnect 1245.

Additionally, one or more memory controllers 1223-1225 are provided to communicate with memory 1233 and 1231 on behalf of the cores and/or matrix operations circuitry.

FIG. 13 illustrates an embodiment of a processor core pipeline supporting matrix operations using tiles. Branch prediction and decode circuitry 1303 performs branch predicting of instructions, decoding of instructions, and/or both from instructions stored in instruction storage 1301. For example, instructions detailed herein may be stored in instruction storage. In some implementations, separate circuitry is used for branch prediction and in some embodiments, at least some instructions are decoded into one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals using microcode 1305. The branch prediction and decode circuitry 1303 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc.

The branch prediction and decode circuitry 1303 is coupled to a rename/allocator circuitry 1307 which is coupled, in some embodiments, to scheduler circuitry 1309. In some embodiments, these circuits provide register renaming, register allocation, and/or scheduling functionality by performing one or more of: 1) renaming logical operand values to physical operand values (e.g., a register alias table in some embodiments), 2) allocating status bits and flags to the decoded instruction, and 3) scheduling the decoded instruction for execution on execution circuitry out of an instruction pool (e.g., using a reservation station in some embodiments).

The scheduler circuitry 1309 represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) scheduler circuitry 1309 is coupled to, or includes, physical register file(s) 1315. Each of the physical register file(s) 1315 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), tiles, etc. In one embodiment, the physical register file(s) 1315 comprises vector registers circuitry, write mask registers circuitry, and scalar registers circuitry. These register circuits may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) 1315 is overlapped by a retirement circuit 1317 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement circuit 1317 and the physical register file(s) 1315 are coupled to the execution circuit(s) 1311.

While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor may also include separate instruction and data cache units and a shared L2 cache unit, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.

The execution circuitry 1311 a set of one or more execution circuits 1321, 1323, and 1327 and a set of one or more memory access circuits 1325. The execution circuits 1321, 1323, and 1327 perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scalar circuitry 1321 performs scalar operations, the vector/SIMD circuitry 1323 performs vector/SIMD operations, and matrix operations circuitry 1327 performs matrix (tile) operations detailed herein.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement a pipeline as follows: 1) an instruction fetch circuit performs fetch and length decoding stages; 2) the branch and decode circuitry 1303 performs a decode stage; 3) the rename/allocator circuitry 1307 performs an allocation stage and renaming stage; 4) the scheduler circuitry 1309 performs a schedule stage; 5) physical register file(s) (coupled to, or included in, the scheduler circuitry 1307 and rename/allocate circuitry 1307 and a memory unit perform a register read/memory read stage; the execution circuitry 1311 performs an execute stage; 6) a memory unit and the physical register file(s) unit(s) perform a write back/memory write stage; 7) various units may be involved in the exception handling stage; and 8) a retirement unit and the physical register file(s) unit(s) perform a commit stage.

The core may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif.; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, Calif.), including the instruction(s) described herein. In one embodiment, the core 1390 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.

It should be understood that the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel® Hyperthreading technology).

FIG. 14 illustrates an embodiment of a processor core pipeline supporting matrix operations using tiles. Branch prediction and decode circuitry 1403 performs branch predicting of instructions, decoding of instructions, and/or both from instructions stored in instruction storage 1401. For example, instructions detailed herein may be stored in instruction storage. In some implementations, separate circuitry is used for branch prediction and in some embodiments, at least some instructions are decoded into one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals using microcode 1405. The branch prediction and decode circuitry 1403 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc.

The branch prediction and decode circuitry 1403 is coupled to a rename/allocator circuitry 1407 which is coupled, in some embodiments, to scheduler circuitry 1409. In some embodiments, these circuits provide register renaming, register allocation, and/or scheduling functionality by performing one or more of: 1) renaming logical operand values to physical operand values (e.g., a register alias table in some embodiments), 2) allocating status bits and flags to the decoded instruction, and 3) scheduling the decoded instruction for execution on execution circuitry out of an instruction pool (e.g., using a reservation station in some embodiments).

The scheduler circuitry 1409 represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) scheduler circuitry 1409 is coupled to, or includes, physical register file(s) 1415. Each of the physical register file(s) 1415 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), tiles, etc. In one embodiment, the physical register file(s) 1415 comprises vector registers circuitry, write mask registers circuitry, and scalar registers circuitry. These register circuits may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) 1415 is overlapped by a retirement circuit 1417 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement circuit 1417 and the physical register file(s) 1415 are coupled to the execution circuit(s) 1411.

While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor may also include separate instruction and data cache units and a shared L2 cache unit, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.

The execution circuitry 1411 a set of one or more execution circuits 1427 and a set of one or more memory access circuits 1425. The execution circuits 1427 perform matrix (tile) operations detailed herein.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement a pipeline as follows: 1) an instruction fetch circuit performs fetch and length decoding stages; 2) the branch and decode circuitry 1403 performs a decode stage; 3) the rename/allocator circuitry 1407 performs an allocation stage and renaming stage; 4) the scheduler circuitry 1409 performs a schedule stage; 5) physical register file(s) (coupled to, or included in, the scheduler circuitry 1407 and rename/allocate circuitry 1407 and a memory unit perform a register read/memory read stage; the execution circuitry 1411 performs an execute stage; 6) a memory unit and the physical register file(s) unit(s) perform a write back/memory write stage; 7) various units may be involved in the exception handling stage; and 8) a retirement unit and the physical register file(s) unit(s) perform a commit stage.

The core may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif.; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, Calif.), including the instruction(s) described herein. In one embodiment, the core 1490 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.

It should be understood that the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel® Hyperthreading technology).

B. Layout

Throughout this description, data is expressed using row major data layout. Column major users should translate the terms according to their orientation. FIG. 15 illustrates an example of a matrix expressed in row major format and column major format. As shown, matrix A is a 2×3 matrix. When this matrix is stored in row major format, the data elements of a row are consecutive. When this matrix is stored in column major format, the data elements of a column are consecutive. It is a well-known property of matrices that A^(T)*B^(T)=(BA)^(T), where superscript T means transpose. Reading column major data as row major data results in the matrix looking like the transpose matrix.

In some embodiments, row-major semantics are utilized in hardware, and column major data is to swap the operand order with the result being transposes of matrix, but for subsequent column-major reads from memory it is the correct, non-transposed matrix.

For example, if there are two column-major matrices to multiply:

$\begin{matrix} {ab} & {gik} & {{ag} + {{bh}\mspace{14mu} {ai}} + {{bj}\mspace{14mu} {ak}} + {bl}} \\ {cd}^{*} & {{hjl} =} & {{cg} + {{dh}\mspace{14mu} {ci}} + {{dj}\mspace{14mu} {ck}} + {dl}} \\ {ef} & \; & {{eg} + {{fh}\mspace{14mu} {ei}} + {{fj}\mspace{14mu} {ek}} + {fl}} \\ \left( {3 \times 2} \right) & \left( {2 \times 3} \right) & \left( {3 \times 3} \right) \end{matrix}$

The input matrices would be stored in linear memory (column-major) as:

acebdf and ghijkl.

Reading those matrices as row-major with dimensions 2×3 and 3×2, they would appear as:

$\begin{matrix} {ace} & {and} & {gh} \\ {bdf} & {ij} & \; \\ {kl} & \; & \; \end{matrix}$

Swapping the order and matrix multiplying:

$\begin{matrix} {gh} & {ace} & {{ag} + {{bh}\mspace{14mu} {cg}} + {{dh}\mspace{14mu} {eg}} + {fh}} \\ {ij}^{*} & {{bdf} =} & {{ai} + {{bj}\mspace{14mu} {ci}} + {{dj}\mspace{14mu} {ei}} + {fj}} \\ {kl} & \; & {{ak} + {{bl}\mspace{14mu} {ck}} + {{dl}\mspace{14mu} {ek}} + {fl}} \end{matrix}$

the transpose matrix is out and can then be stored in in row-major order:

ag + cg + eg + ai + ci + ei + ak + ck + ek + bh dh fh bj dj fj bl dl fl and used in subsequent column major computations, it is the correct un-transposed matrix:

ag + bh ai + bj ak + bl cg + dh ci + dj ck + dl eg + fh ei + fj ek + fl

III. Exemplary Usage

FIG. 16 illustrates an example of usage of matrices (tiles). In this example, matrix C 1601 includes two tiles, matrix A 1603 includes one tile, and matrix B 1605 includes two tiles. This figure shows an example of the inner loop of an algorithm to compute a matrix multiplication. In this example, two result tiles, tmm0 and tmm1, from matrix C 1601 are used to accumulate the intermediate results. One tile from the matrix B1603 (tmm2) is re-used twice as it multiplied by two tiles from the matrix B 1605. Pointers to load a new A tile and two new B tiles from the directions indicated by the arrows. An outer loop, not shown, adjusts the pointers for the C tiles.

The exemplary code as shown includes the usage of a tile configuration instruction and is executed to configure tile usage, load tiles, a loop to process the tiles, store tiles to memory, and release tile usage.

FIG. 17 illustrates an embodiment of usage of matrices (tiles). At 1701, tile usage is configured. For example, a TILECONFIG instruction is executed to configure tile usage including setting a number of rows and columns per tile. Typically, at least one matrix (tile) is loaded from memory at 1703. At least one matrix (tile) operation is performed at 1705 using the matrices (tiles). At 1707, at least one matrix (tile) is stored out to memory and a context switch can occur at 1709.

IV. Exemplary Configuration

A. Tile Configuration Hardware Support

As discussed above, tile usage typically needs to be configured prior to use. For example, full usage of all rows and columns may not be needed. Not only does not configuring these rows and columns save power in some embodiments, but the configuration may be used to determine if an operation will generate an error. For example, a matrix multiplication of the form (N×M)*(L*N) will typically not work if M and L are not the same.

Prior to using matrices using tiles, in some embodiments, tile support is to be configured. For example, how many rows and columns per tile, tiles that are to be used, etc. are configured. A TILECONFIG instruction is an improvement to a computer itself as it provides for support to configure the computer to use a matrix accelerator (either as a part of a processor core, or as an external device). In particular, an execution of the TILECONFIG instruction causes a configuration to be retrieved from memory and applied to matrix (tile) settings within a matrix accelerator.

i. TILE USAGE CONFIGURATION

FIG. 18 illustrates support for configuration of the usage of tiles according to an embodiment. A memory 1801 contains the description of the matrices (tiles) to be supported 1803.

Execution circuitry 1811 of a processor/core 1805 stores aspects of a tile description 1803 into tile configurations 1817. The tile configurations 1817 detail what tiles for a palette are configured (the number of rows and columns in each tile) and a marking that matrix support is in use. In particular, instruction execution resources 1811 are configured to use tiles as specified by the tile configuration 1817. The instruction execution resources may also include a machine specific register or configuration register to indicate tile usage. Additional values such as in-use and start values are also set. The tile configurations 1817 utilize one or more registers 1819 to store tile usage and configuration information.

FIG. 19 illustrates an embodiment of a description of the matrices (tiles) to be supported. This is the description that is to be stored upon an execution of a STTILECFG instruction. In this example, each field is a byte. In byte[0], a palette ID 1901 is stored. The palette ID is used to index a palette table 1813 which stores, per palette ID, a number of bytes in a tile, and bytes per row of the tiles that are associated with this ID as defined by the configuration.

Byte 1 stores a value to be stored in a “startRow” register 1903 and byte 2 stores a value to be stored in a “startP” register 1905. To support restarting instructions after these events, the instructions store information these registers. To support restarting instructions after break events such as those detailed above, the instructions store information in these registers. The startRow value indicates the row that should be used for restart. The startP value indicates the position within the row for store operations when pairs are used and, in some embodiments, indicates the lower half of the row (in the lower tile of a pair) or higher half of the row (in the higher tile of a pair). Generally, the position in the row (the column) is not needed.

With the exception of TILECONFIG and STTILECFG, successfully executing matrix (tile) instructions will set both startRow and startP to zero.

Any time an interrupted matrix (tile) instruction is not restarted, it is the responsibility of software to zero the startRow and startP values. For example, unmasked floating point exception handlers might decide to finish the operation in software and change the program counter value to another instruction, usually the next instruction. In this case the software exception handler must zero the startRow and startP values in the exception presented to it by the operating system before resuming the program. The operating system will subsequently reload those values using a restore instruction.

Byte 3 stores an indication of pairs (1b per tile) of tiles 1907.

Bytes 16-17 store the number of rows 1913 and columns 1915 for tile 0, bytes 18-19 store the number of rows and columns for tile 1, etc. In other words, each 2 byte group specifies a number of rows and columns for a tile. If a group of 2 bytes is not used to specify tile parameters, they should have the value zero. Specifying tile parameters for more tiles than the implementation limit or the palette limit results in a fault. Unconfigured tiles are set to an initial state with 0 rows, 0 columns.

Finally, the configuration in memory typically ends with an ending delineation such as all zeros for several consecutive bytes.

ii. EXEMPLARY TILE AND TILE CONFIGURATION STORAGE

FIGS. 20(A)-(D) illustrate examples of register(s) 1819. FIG. 20(A) illustrates a plurality of registers 1819. As shown each tile (TMM0 2001 . . . TMMN 2003) has a separate register with each register storing a row and column size for that particular tile. StartP and StartRow are stored in separate registers 2011 and 2013. One or more status registers 2015 are set (e.g., TILES_CONFIGURED=1) to indicate tiles are configured for use.

FIG. 20(B) illustrates a plurality of registers 1819. As shown each tile has separate registers for its rows and columns. For example, TMM0 rows configuration 2021, TMM0 columns configuration 2023, StartP and StartRow are stored in separate registers 2011 and 2013. One or more status registers 2015 are set (e.g., TILES_CONFIGURED=1) to indicate tiles are configured for use.

FIG. 20(C) illustrates a single register 1819. As shown, this register stores tile configurations (rows and columns per tile) 2031, StartP 2011, and StartRow 2013 are stored in single register as packed data registers. One or more status registers 2015 are set (e.g., TILES_CONFIGURED=1) to indicate tiles are configured for use.

FIG. 20(D) illustrates a plurality of registers 1819. As shown, a single register stores tile configurations (rows and columns per tile) 2031. StartP and StartRow are stored in separate registers 2011 and 2013. One or more status registers 2015 are set (e.g., TILES_CONFIGURED=1) to indicate tiles are configured for use.

Other combinations are contemplated such as combining the start registers into a single register where they are shown separately, etc.

B. Tile Dot Product

Detailed herein are embodiments of a matrix (tile) dot product (“TDPPAIR”) instruction and their execution. A TDPPAIR instruction is an improvement to a computer itself as it provides for support to perform dot product operations involving at least two matrices (tiles) of data values with a single instruction. In particular, the execution of a TDPPAIR instruction causes performance of dot product operations on elements from two source matrices (tiles) of data values and accumulation of the result into corresponding data element positions of a destination matrix pair (tile pair). The size of the data elements in the source matrices (tiles) varies depending on the instruction and tile support. Exemplary sizes of the data elements contained in the source matrices (tiles) include, but are not limited to, 4-bit, 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, 256-bit, and so forth. The data element sizes of the destination matrix pair (tile pair) are greater than the data element sizes of the source matrices (tiles). In some embodiments, elements of rows and columns of the destination matrix pair (tile pair) that do not have corresponding elements in the source matrices (tiles) are zeroed.

i. EXEMPLARY EXECUTION

FIG. 21 illustrates an exemplary execution of a TDPPAIR instruction. The TDPPAIR instruction format includes fields for an opcode (e.g., shown as “TDP” in the figure), a destination matrix pair (tile pair) operand (e.g., shown as “DESTINATION MATRIX PAIR (TILE PAIR)” in the figure), and two source operands (e.g., shown as “FIRST SOURCE MATRIX (TILE)” and “SECOND SOURCE MATRIX (TILE)” in the figure). In an embodiment, the destination matrix pair (tile pair) operand is used to accumulate the data resulting from performing dot product operations on elements of the first and second source matrix (tile) operands. An example destination matrix pair (tile pair) operand 2101 is shown in FIG. 21, initially storing a matrix of quadword-sized data elements.

In some embodiments, a pair of tiles comprises a first tile being a first half of the columns of a matrix and a second tile being a second half of the columns of the matrix, wherein the columns of the matrix are consecutive columns of each tile. For example, in some embodiments, a first matrix (tile) makes up the lower half of each row of the destination matrix pair (tile pair) operand 2101 and a second matrix (tile) makes up the upper half of each row of the destination matrix pair (tile pair) operand 2101.

In some embodiments, a pair of tiles comprises a first tile being a first half of the rows of a matrix and a second tile being a second half of the rows of the matrix, wherein the columns of the matrix are consecutive rows of each tile. For example, in some embodiments, a first matrix (tile) makes up the lower half of the columns of the destination matrix pair (tile pair) operand 2101 and a second matrix (tile) makes up the upper half of the columns of the destination matrix pair (tile pair) operand 2101.

In some embodiments, a pair of tiles comprises a first tile being a first half of the columns of a matrix and a second tile being a second half of the columns of the matrix, wherein the columns of the matrix are interleaved columns of each tile. In some embodiments, a pair of tiles comprises a first tile being a first half of the rows of a matrix and a second tile being a second half of the rows of the matrix, wherein the columns of the matrix are interleaved rows of each tile.

The two source matrix (tile) operand fields represent a first source matrix (tile) operand 2103 and a second source matrix (tile) operand 2105, respectively. As detailed earlier, a matrix (tile) may be stored in a collection of registers, locations in memory (for example, as strided rows), or in storage accessible to execution circuitry. In some embodiments, the data elements of the first source matrix (tile) operand 2103 and the second source matrix (tile) operand 2105 are doublewords comprising two word sub-elements.

In FIG. 21, each of the destination matrix pair (tile pair) operand 2101, the first source matrix (tile) operand 2103, and the second source matrix (tile) operand 2105 comprises a 2×2 matrix of data elements. The dimensions of the matrices in FIG. 21 are used for illustrative purposes only; in general, a TDPIAR instruction can operate on any two source matrix (tile) operands where the number of columns associated with a first matrix (tile) operand is the same as the number of rows of a second matrix (tile) operand (that is, where the dimensions of a first matrix (tile) operand is M rows×K columns and the dimensions of a second matrix (tile) operand is K rows×N columns, as shown in FIG. 21). The destination matrix pair (tile pair) operand in this example has M rows×N columns such that the number of rows in the destination matrix pair (tile pair) is the same as the number of rows in the first matrix (tile) operand and the number of columns in the destination matrix pair (tile pair) is the same as the number of columns in the second matrix (tile) operand.

As shown, execution circuitry 2107 uses a grid of fused multiply adders (FMAs) 2109 to execute a decoded TDPPAIR instruction by performing dot product operations on elements of the two source matrix (tile) operands 2103 and 2105 and accumulating the result into corresponding data element positions of the destination matrix pair (tile pair) operand 2101. Each data element in the twos source matrix (tile) operands 2103 and 2105 comprises two sub-elements to use in the dot product operation. In some embodiments, each of these sub-elements are sign extended prior to the dot product operation.

Referring to the example destination matrix pair (tile pair) operand 2101 and source matrix (tile) operands 2103 and 2105, the execution circuitry 2107 generates dot product values using the first row of the first source matrix (tile) operand 2103 and the first column of the second source matrix (tile) operand 2105 and accumulates the result in the [0,0] data element position of the destination matrix (tile) operand 2101. In FIG. 21, for example, the [0,0] data element position of the destination matrix (tile) operand 2101 accumulates the initially stored value W with dot product values computed using the first row of the first source matrix (tile) operand 2103 (the sub-elements [A,B] and [C,D]) and the first column of the second source matrix (tile) operand 2105 (the sub-elements [I,J] and [M,N]), that is, W+((A*I)+(B*J))+((C*M)+(D*N]), where W is a quadword value and A, B, C, D, I, J, M, and N are 16-bit values).

The execution circuitry 2107 further computes dot product values using the first row of the first source matrix (tile) operand 2103 and the second column of the second source matrix (tile) operand 2105 and accumulates the result in the [0,1] data element position of the destination matrix (tile) operand 2101. The execution circuitry 2107 further generates dot product values using the second row of the first source matrix (tile) operand 2103 and the first column of the second matrix (tile) operand 2105 and accumulates the result in the [1,0] data element position of the destination matrix (tile) operand 2101. The execution circuitry 2107 further generates dot product values using the second row of the first source matrix (tile) operand 2103 and the second column of the second source matrix (tile) operand 2105 and accumulates the result in the [1,1] data element position of the destination matrix (tile) operand 2101.

ii. EXEMPLARY FORMAT(S)

One embodiment of a format for a TDPPAIR instruction is TDPQWSSQPAIR TMM1[+1], TMM2, TMM3. In some embodiments, TDPQWSSQPAIR is the opcode mnemonic of the instruction, where the “TDP” part of the mnemonic indicates a tile dot product operation and the “QWSSQPAIR” part of the mnemonic indicates that the instruction computes the dot product of source matrix (tile) operands comprising signed word-sized sub-elements and accumulates the result into a destination matrix (tile) comprising quadword-sized elements. In this instruction format and the instruction formats below, TMM1[+1] is a field for identifying the destination matrix (tile) operand. TMM2 and TMM3 are fields for identifying the matrix (tile) source operands. In some embodiments, the TMM2 field is a R/M value (such as 2546), the TMM1 field is REG 2544, TMM3 is 2522.

In embodiments, encodings of the instruction include a scale-index-base (SIB) type memory addressing operand that indirectly identifies multiple indexed destination locations in memory. In one embodiment, an SIB type memory operand may include an encoding identifying a base address register. The contents of the base address register may represent a base address in memory from which the addresses of the particular destination locations in memory are calculated. For example, the base address may be the address of the first location in a block of potential destination locations for an extended vector instruction. In one embodiment, an SIB type memory operand may include an encoding identifying an index register. Each element of the index register may specify an index or offset value usable to compute, from the base address, an address of a respective destination location within a block of potential destination locations. In one embodiment, an SIB type memory operand may include an encoding specifying a scaling factor to be applied to each index value when computing a respective destination address. For example, if a scaling factor value of four is encoded in the SIB type memory operand, each index value obtained from an element of the index register may be multiplied by four and then added to the base address to compute a destination address.

In one embodiment, an SIB type memory operand of the form vm32{x,y,z} may identify a vector array of memory operands specified using SIB type memory addressing. In this example, the array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements, each of which is a 32-bit index value. The vector index register may be a 128-bit register (e.g., XMM) register (vm32x), a 256-bit (e.g., YMM) register (vm32y), or a 512-bit (e.g., ZMM) register (vm32z). In another embodiment, an SIB type memory operand of the form vm64{x,y,z} may identify a vector array of memory operands specified using SIB type memory addressing. In this example, the array of memory addresses is specified using a common base register, a constant scaling factor, and a vector index register containing individual elements, each of which is a 64-bit index value. The vector index register may be a 128-bit register (e.g., XMM) register (vm64x), a 256-bit (e.g., YMM) register (vm64y) or a 512-bit (e.g., ZMM) register (vm64z).

iii. EXEMPLARY METHOD(S) OF EXECUTION

FIG. 22 illustrates an embodiment of method performed by a processor to process a matrix (tile) dot product instruction.

At 2201, an instruction is fetched. For example, a TDPPAIR instruction is fetched. The TDPPAIR instruction includes fields for an opcode, a first and a second source matrix (tile) operand, and a destination matrix pair (tile pair) operand. In some embodiments, the instruction further includes a field for a writemask. In some embodiments, the instruction is fetched from an instruction cache. The source operands and destination operand consist of packed data. The opcode of the TDPPAIR instruction indicates that a dot product operation is to be performed on the source matrix (tile) operands. In some embodiments, the opcode further indicates whether each of the first source matrix (tile) operand and second source matrix (tile) operand consist signed or unsigned values. In some embodiments, the opcode further indicates a size (for example, a specified number of bits, bytes, quadwords, doublewords, and so forth) of the matrix (tile) data values comprising each of the first source matrix (tile) operand, the second source matrix (tile) operand, and the destination matrix pair (tile pair) operand.

The fetched instruction is decoded at 2203. For example, the fetched TDPPAIR instruction is decoded by decode circuitry such as that detailed herein.

Data values associated with the source matrix (tile) operands of the decoded instruction are retrieved at 2205 and the decoded instruction is scheduled (as needed). For example, when one or more of the source matrix (tile) operands are memory operands, the data from the indicated memory location is retrieved.

At 2207, the decoded instruction is executed by execution circuitry (hardware) such as that detailed herein. For the TDPPAIR instruction, the execution causes execution circuitry to perform a dot product operation on source data. In some embodiments, the execution of a decoded matrix dot product instruction causes an execution circuit to: compute a result by performing dot product operations on elements from the first source matrix and the second source matrix operand; and accumulate the result into elements of the destination matrix operand. In some embodiments, each element of the first and second source matrix comprises two sub-elements that are word size. In some embodiments, data elements of the destination matrix pair (tile pair) that are not written are zeroed.

In some embodiments, a fault is generated when one or more of the following is true: a number of columns associated with the first source matrix operand is different than a number of rows associated with the second source matrix operand; a number of rows associated with the destination matrix pair (tile pair) operand is different than a number of rows associated with the first source matrix (tile) operand; and a number of columns associated with the destination matrix pair (tile pair) operand is different than a number of columns associated with the second source matrix (tile) operand.

In some embodiments, the instruction is committed or retired at 2209.

FIG. 23 illustrates additional detailed related to an example method performed by a processor to execute a TDPPAIR instruction, where the instruction has fields for a first source matrix (tile) operand, a second source matrix (tile) operand, and a destination matrix pair (tile pair) operand according to an embodiment.

At 2301, execution circuitry sets a first counter with the value zero. At 2302, it is determined whether the first counter is less than a number of configured rows of the destination matrix pair (tile pair) operand. If the first counter is not less than the number of configured rows of the destination matrix pair (tile pair) operand, the process ends.

At 2303, if the first counter is less than the number of configured rows of the destination matrix pair (tile pair) operand, a second counter is set with the value zero. At 2304, it is determined whether the second counter is less than a number of configured columns of a first source matrix (tile) operand. If not, the first counter is incremented at 2312 and the process returns to 2302.

At 2305, if the second counter is less than a number of configured columns of the first source matrix (tile) operand, a row from the destination matrix pair (tile pair) operand identified by the first counter is written to a temporary location. For example, if the first counter is currently set to zero, then row[first counter] identifies the first row of the destination matrix pair (tile pair) operand. Similarly, if the first counter is currently set to one, then row[first counter] identifies the second row of the destination matrix pair (tile pair) operand, and so forth. At 2306, a third counter is set with the value zero.

At 2307, it is determined whether the third counter is less than a number of configured columns of the destination matrix operand. If the third counter is not less than the number of configured columns of the destination matrix pair (tile pair) operand, at 2310, the data values stored at the temporary location are written to a row of the destination matrix pair (tile pair) operand identified by the first counter (that is, the row[first counter] of the destination matrix pair (tile pair) operand). At 2311, the second counter is incremented and the process returns to 2304.

If the third counter is less than the number of configured columns of the destination matrix pair (tile pair) accumulator operand, at 2308, the execution circuitry performs a dot product operation involving data elements of the first source matrix (tile) operand at position row[first counter, second counter] and data elements of the second source matrix (tile) operand at position row[second counter, third counter] and accumulates the result at the element position[third counter] of the temporary location. In reference to FIG. 21, and assuming each of the first counter, the second counter, and the third counter is currently set to zero, a dot product operation is performed at 2308 involving the data elements of the first source matrix (tile) operand 2102 at position row[0,0] (the element values [A,B]) and data elements of the second source matrix (tile) operand 2103 at position row[0,0] (the element values [I,J]) and accumulates the result at the element position[0] of the temporary location (currently storing the value W from the row[0,0] of the destination matrix pair (tile pair) operand 2101).

At 2309, the third counter is incremented and the process returns to 2307. The result of the process described in FIG. 23 is the performance of dot product operations on elements from the first source matrix (tile) operand and the second source matrix (tile) operand and the accumulation of the results into elements of the destination matrix pair (tile pair) accumulator operand, as illustrated in the destination matrix (tile) operand 2101 of FIG. 21.

FIG. 24 illustrates an example of methods for performing tile dot products operations, as described above, according to an embodiment. For example, the steps shown in 2401 and 2403 illustrate an example process for performing an operation involving source matrices of signed word-sized elements accumulated into doubleword-sized elements with saturation (for example, based on an instruction of the example format TDPWSSDS TMM1[+1], TMM2, TMM3). In particular, 2401 illustrates an example helper process DPWSSQPAIR(c, x, y) used to perform a multiply and add operation on doubleword and quadword arguments. As shown in the accompanying process 2403, the multiply and add operation illustrated in 2401 is used as part of the dot product calculations performed on the rows and columns of the source matrix (tile) operands.

The processor of 2403 indicates when a fault is generated. The process of 2403 iterates through the rows and columns of the destination matrix pair (tile pair) and source matrices (tiles). In particular, the example process computes a result by performing dot product operations on elements from a first source matrix (tile) operand (“tsrc1”) and a second source matrix (tile) operand (“tsrc2”) and accumulates the result into elements of the destination matrix pair (tile pair) operand (“tsrcdest”).

iv. EXAMPLES Example 1

A processor comprising: decode circuitry to decode an instruction having fields to identify a first source matrix operand, a second source matrix operand, and a destination matrix pair operand; and execution circuitry to execute the decoded instruction to: compute a result by performing dot product operations on data elements from the identified first source matrix operand and the identified second source matrix operand, and accumulate the result into data element positions of the destination matrix pair operand, wherein data element positions of the destination matrix pair operand are larger than a size of the data elements of the identified first source matrix operand and the identified second source matrix operand.

Example 2

The processor of example 1, wherein the elements of the identified first source matrix operand and the identified second source matrix operand are signed doubleword elements, and wherein the elements of the identified destination matrix operand are quadwords.

Example 3

The processor of any of examples 1-2, wherein the execution circuitry comprises a plurality of fused-multiply adders.

Example 4

The processor of any of examples 1-3, wherein the identified destination matrix pair operand comprises a pair of groups of packed data registers.

Example 5

The processor of example 4, wherein a first group of the pair of groups of packed data registers is to store a first half of consecutive columns of a matrix and a second group of the pair of groups of packed data registers is to store a first half of consecutive columns of the matrix.

Example 6

The processor of example 4, wherein a first group of the pair of groups of packed data registers is to store a first half of consecutive rows of a matrix and a second group of the pair of groups of packed data registers is to store a first half of consecutive rows of the matrix.

Example 7

The processor of example 4, wherein a first group of the pair of groups of packed data registers is to store a first half of interleaved columns of a matrix and a second group of the pair of groups of packed data registers is to store a first half of interleaved columns of the matrix.

Example 8

The processor of example 4, wherein a first group of the pair of groups of packed data registers is to store a first half of interleaved rows of a matrix and a second group of the pair of groups of packed data registers is to store a first half of interleaved rows of the matrix.

Example 9

The processor of any of examples 1-8, wherein a fault is generated when a number of rows of the identified destination matrix pair operand is different than a number of rows of the identified first source matrix operand.

Example 10

The processor of any of examples 1-9, wherein a fault is generated when a number of columns of the identified destination matrix pair operand is different than a number of columns of the identified second source matrix operand.

Example 11

The processor of any of examples 1-10, wherein the execution circuitry is further to zero data element positions that do not have an accumulate value.

Example 12

A method comprising: decoding an instruction having fields to identify a first source matrix operand, a second source matrix operand, and a destination matrix pair operand; and executing the decoded instruction to: compute a result by performing dot product operations on data elements from the identified first source matrix operand and the identified second source matrix operand, and accumulate the result into data element positions of the destination matrix pair operand, wherein data element positions of the destination matrix pair operand are larger than a size of the data elements of the identified first source matrix operand and the identified second source matrix operand.

Example 13

The method of example 12, wherein the elements of the identified first source matrix operand and the identified second source matrix operand are signed doubleword elements, and wherein the elements of the identified destination matrix operand are quadwords.

Example 14

The method of any of examples 12-13, wherein the executing uses a plurality of fused-multiply adders.

Example 15

The method of any of examples 12-14, wherein the identified destination matrix pair operand comprises a pair of groups of packed data registers.

Example 16

The method of example 15, wherein a first group of the pair of groups of packed data registers is to store a first half of consecutive columns of a matrix and a second group of the pair of groups of packed data registers is to store a first half of consecutive columns of the matrix.

Example 17

The method of example 15, wherein a first group of the pair of groups of packed data registers is to store a first half of consecutive rows of a matrix and a second group of the pair of groups of packed data registers is to store a first half of consecutive rows of the matrix.

Example 18

The method of example 15, wherein a first group of the pair of groups of packed data registers is to store a first half of interleaved columns of a matrix and a second group of the pair of groups of packed data registers is to store a first half of interleaved columns of the matrix.

Example 19

The method of example 15, wherein a first group of the pair of groups of packed data registers is to store a first half of interleaved rows of a matrix and a second group of the pair of groups of packed data registers is to store a first half of interleaved rows of the matrix.

Example 20

The method of any of examples 12-19, wherein a fault is generated when a number of rows of the identified destination matrix pair operand is different than a number of rows of the identified first source matrix operand.

Example 21

The method of any of examples 12-20, wherein a fault is generated when a number of columns of the identified destination matrix pair operand is different than a number of columns of the identified second source matrix operand.

Example 22

The method of any of examples 12-21, wherein the executing is further to zero data element positions that do not have an accumulate value.

Example 23

A non-transitory machine-readable medium according to execute the method according to examples 12-22.

Example 22

A system according to examples 1-11 and further including memory to store the instruction.

Detailed below are exemplary instruction formats, pipelines, systems, processors, etc. that support a tile dot product instruction.

An instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, location of bits) to specify, among other things, the operation to be performed (opcode) and the operand(s) on which that operation is to be performed. Some instruction formats are further broken down though the definition of instruction templates (or subformats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands.

Exemplary Instruction Formats

Embodiments of the instruction(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.

VEX Instruction Format

VEX encoding allows instructions to have more than two operands, and allows SIMD vector registers to be longer than 258 bits. The use of a VEX prefix provides for three-operand (or more) syntax. For example, previous two-operand instructions performed operations such as A=A+B, which overwrites a source operand. The use of a VEX prefix enables operands to perform nondestructive operations such as A=B+C.

FIG. 25A illustrates an exemplary instruction format including a VEX prefix 2502, real opcode field 2530, Mod RIM byte 2540, SIB byte 2550, displacement field 2562, and IMM8 2572. FIG. 25B illustrates which fields from FIG. 25A make up a full opcode field 2574 and a base operation field 2541. FIG. 25C illustrates which fields from FIG. 25A make up a register index field 2544.

VEX Prefix (Bytes 0-2) 2502 is encoded in a three-byte form. The first byte is the Format Field 2590 (VEX Byte 0, bits [7:0]), which contains an explicit C4 byte value (the unique value used for distinguishing the C4 instruction format). The second-third bytes (VEX Bytes 1-2) include a number of bit fields providing specific capability. Specifically, REX field 2505 (VEX Byte 1, bits [7-5]) consists of a VEX.R bit field (VEX Byte 1, bit [7]-R), VEX.X bit field (VEX byte 1, bit [6]-X), and VEX.B bit field (VEX byte 1, bit[5]-B). Other fields of the instructions encode the lower three bits of the register indexes as is known in the art (rrr, xxx, and bbb), so that Rrrr, Xxxx, and Bbbb may be formed by adding VEX.R, VEX.X, and VEX.B. Opcode map field 2515 (VEX byte 1, bits [4:0]-mmmmm) includes content to encode an implied leading opcode byte. W Field 2564 (VEX byte 2, bit [7]-W)—is represented by the notation VEX.W, and provides different functions depending on the instruction. The role of VEX.vvvv 2520 (VEX Byte 2, bits [6:3]-vvvv) may include the following: 1) VEX.vvvv encodes the first source register operand, specified in inverted (1s complement) form and is valid for instructions with 2 or more source operands; 2) VEX.vvvv encodes the destination register operand, specified in 1s complement form for certain vector shifts; or 3) VEX.vvvv does not encode any operand, the field is reserved and should contain 1111b. If VEX.L 2568 Size field (VEX byte 2, bit [2]-L)=0, it indicates 258 bit vector; if VEX.L=1, it indicates 256 bit vector. Prefix encoding field 2525 (VEX byte 2, bits [1:0]-pp) provides additional bits for the base operation field 2541.

Real Opcode Field 2530 (Byte 3) is also known as the opcode byte. Part of the opcode is specified in this field.

MOD RIM Field 2540 (Byte 4) includes MOD field 2542 (bits [7-6]), Reg field 2544 (bits [5-3]), and RIM field 2546 (bits [2-0]). The role of Reg field 2544 may include the following: encoding either the destination register operand or a source register operand (the rrr of Rrrr), or be treated as an opcode extension and not used to encode any instruction operand. The role of R/M field 2546 may include the following: encoding the instruction operand that references a memory address, or encoding either the destination register operand or a source register operand.

Scale, Index, Base (SIB)—The content of Scale field 2550 (Byte 5) includes SS2552 (bits [7-6]), which is used for memory address generation. The contents of SIB.xxx 2554 (bits [5-3]) and SIB.bbb 2556 (bits [2-0]) have been previously referred to with regard to the register indexes Xxxx and Bbbb.

The Displacement Field 2562 and the immediate field (IMM8) 2572 contain data.

Exemplary Register Architecture

FIG. 26 is a block diagram of a register architecture 2600 according to one embodiment of the invention. In the embodiment illustrated, there are 32 vector registers 2610 that are 512 bits wide; these registers are referenced as zmm0 through zmm31. The lower order 256 bits of the lower 29 zmm registers are overlaid on registers ymm0-15. The lower order 128 bits of the lower 29 zmm registers (the lower order 128 bits of the ymm registers) are overlaid on registers xmm0-15.

General-purpose registers 2625—in the embodiment illustrated, there are sixteen 64-bit general-purpose registers that are used along with the existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

Scalar floating point stack register file (x87 stack) 2645, on which is aliased the MMX packed integer flat register file 2650—in the embodiment illustrated, the x87 stack is an eight-element stack used to perform scalar floating-point operations on 32/64/80-bit floating point data using the x87 instruction set extension; while the MMX registers are used to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.

Alternative embodiments of the invention may use wider or narrower registers. Additionally, alternative embodiments of the invention may use more, less, or different register files and registers.

Exemplary Core Architectures, Processors, and Computer Architectures

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high performance general purpose out-of-order core intended for general-purpose computing; 3) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die in the same package as a CPU; 3) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and 4) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures. Detailed herein are circuits (units) that comprise exemplary cores, processors, etc.

Exemplary Core Architectures

In-Order and Out-of-Order Core Block Diagram

FIG. 27A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention. FIG. 27B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention. The solid lined boxes in FIGS. 27A-B illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

In FIG. 27A, a processor pipeline 2700 includes a fetch stage 2702, a length decode stage 2704, a decode stage 2706, an allocation stage 2708, a renaming stage 2710, a scheduling (also known as a dispatch or issue) stage 2712, a register read/memory read stage 2714, an execute stage 2716, a write back/memory write stage 2718, an exception handling stage 2722, and a commit stage 2724.

FIG. 27B shows processor core 2790 including a front end unit 2730 coupled to an execution engine unit 2750, and both are coupled to a memory unit 2770. The core 2790 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core 2790 may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front end unit 2730 includes a branch prediction unit 2732 coupled to an instruction cache unit 2734, which is coupled to an instruction translation lookaside buffer (TLB) 2736, which is coupled to an instruction fetch unit 2738, which is coupled to a decode unit 2740. The decode unit 2740 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit 2740 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core 2790 includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit 2740 or otherwise within the front end unit 2730). The decode unit 2740 is coupled to a rename/allocator unit 2752 in the execution engine unit 2750.

The execution engine unit 2750 includes the rename/allocator unit 2752 coupled to a retirement unit 2754 and a set of one or more scheduler unit(s) 2756. The scheduler unit(s) 2756 represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) 2756 is coupled to the physical register file(s) unit(s) 2758. Each of the physical register file(s) units 2758 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit 2758 comprises a vector registers unit and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s) 2758 is overlapped by the retirement unit 2754 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit 2754 and the physical register file(s) unit(s) 2758 are coupled to the execution cluster(s) 2760. The execution cluster(s) 2760 includes a set of one or more execution units 2762 and a set of one or more memory access units 2764. The execution units 2762 may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) 2756, physical register file(s) unit(s) 2758, and execution cluster(s) 2760 are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) 2764). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units 2764 is coupled to the memory unit 2770, which includes a data TLB unit 2772 coupled to a data cache unit 2774 coupled to a level 2 (L2) cache unit 2776. In one exemplary embodiment, the memory access units 2764 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 2772 in the memory unit 2770. The instruction cache unit 2734 is further coupled to a level 2 (L2) cache unit 2776 in the memory unit 2770. The L2 cache unit 2776 is coupled to one or more other levels of cache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline 2700 as follows: 1) the instruction fetch 2738 performs the fetch and length decoding stages 2702 and 2704; 2) the decode unit 2740 performs the decode stage 2706; 3) the rename/allocator unit 2752 performs the allocation stage 2708 and renaming stage 2710; 4) the scheduler unit(s) 2756 performs the schedule stage 2712; 5) the physical register file(s) unit(s) 2758 and the memory unit 2770 perform the register read/memory read stage 2714; the execution cluster 2760 perform the execute stage 2716; 6) the memory unit 2770 and the physical register file(s) unit(s) 2758 perform the write back/memory write stage 2718; 7) various units may be involved in the exception handling stage 2722; and 8) the retirement unit 2754 and the physical register file(s) unit(s) 2758 perform the commit stage 2724.

The core 2790 may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif.; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, Calif.), including the instruction(s) described herein. In one embodiment, the core 2790 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.

It should be understood that the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel® Hyperthreading technology).

While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache units 2734/2774 and a shared L2 cache unit 2776, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.

Specific Exemplary In-Order Core Architecture

FIGS. 28A-B illustrate a block diagram of a more specific exemplary in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and/or different types) in a chip. The logic blocks communicate through a high-bandwidth interconnect network (e.g., a ring network) with some fixed function logic, memory I/O interfaces, and other necessary I/O logic, depending on the application.

FIG. 28A is a block diagram of a single processor core, along with its connection to the on-die interconnect network 2802 and with its local subset of the Level 2 (L2) cache 2804, according to embodiments of the invention. In one embodiment, an instruction decoder 2800 supports the x86 instruction set with a packed data instruction set extension. An L1 cache 2806 allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit 2808 and a vector unit 2810 use separate register sets (respectively, scalar registers 2812 and vector registers 2814) and data transferred between them is written to memory and then read back in from a level 1 (L1) cache 2806, alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

The local subset of the L2 cache 2804 is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache 2804. Data read by a processor core is stored in its L2 cache subset 2804 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 2804 and is flushed from other subsets, if necessary. The ring network ensures coherency for shared data. The ring network is bi-directional to allow agents such as processor cores, L2 caches and other logic blocks to communicate with each other within the chip. Each ring data-path is 1024-bits wide per direction in some embodiments.

FIG. 28B is an expanded view of part of the processor core in FIG. 28A according to embodiments of the invention. FIG. 28B includes an L1 data cache 2806A part of the L1 cache 2804, as well as more detail regarding the vector unit 2810 and the vector registers 2814. Specifically, the vector unit 2810 is a 29-wide vector processing unit (VPU) (see the 16-wide ALU 2828), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit 2820, numeric conversion with numeric convert units 2822A-B, and replication with replication unit 2824 on the memory input.

Processor with Integrated Memory Controller and Graphics

FIG. 29 is a block diagram of a processor 2900 that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention. The solid lined boxes in FIG. 29 illustrate a processor 2900 with a single core 2902A, a system agent 2910, a set of one or more bus controller units 2916, while the optional addition of the dashed lined boxes illustrates an alternative processor 2900 with multiple cores 2902A-N, a set of one or more integrated memory controller unit(s) 2914 in the system agent unit 2910, and special purpose logic 2908.

Thus, different implementations of the processor 2900 may include: 1) a CPU with the special purpose logic 2908 being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 2902A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor with the cores 2902A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores 2902A-N being a large number of general purpose in-order cores. Thus, the processor 2900 may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor 2900 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of cache within the cores 2904A-N, a set or one or more shared cache units 2906, and external memory (not shown) coupled to the set of integrated memory controller units 2914. The set of shared cache units 2906 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit 2912 interconnects the integrated graphics logic 2908, the set of shared cache units 2906, and the system agent unit 2910/integrated memory controller unit(s) 2914, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units 2906 and cores 2902-A-N.

In some embodiments, one or more of the cores 2902A-N are capable of multi-threading. The system agent 2910 includes those components coordinating and operating cores 2902A-N. The system agent unit 2910 may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores 2902A-N and the integrated graphics logic 2908. The display unit is for driving one or more externally connected displays.

The cores 2902A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 2902A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

Exemplary Computer Architectures

FIGS. 30-33 are block diagrams of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

Referring now to FIG. 30, shown is a block diagram of a system 3000 in accordance with one embodiment of the present invention. The system 3000 may include one or more processors 3010, 3015, which are coupled to a controller hub 3020. In one embodiment, the controller hub 3020 includes a graphics memory controller hub (GMCH) 3090 and an Input/Output Hub (IOH) 3050 (which may be on separate chips); the GMCH 3090 includes memory and graphics controllers to which are coupled memory 3040 and a coprocessor 3045; the IOH 3050 is couples input/output (I/O) devices 3060 to the GMCH 3090. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory 3040 and the coprocessor 3045 are coupled directly to the processor 3010, and the controller hub 3020 in a single chip with the IOH 3050.

The optional nature of additional processors 3015 is denoted in FIG. 30 with broken lines. Each processor 3010, 3015 may include one or more of the processing cores described herein and may be some version of the processor 2900.

The memory 3040 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 3020 communicates with the processor(s) 3010, 3015 via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface, or similar connection 3095.

In one embodiment, the coprocessor 3045 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub 3020 may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources 3010, 30155 in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

In one embodiment, the processor 3010 executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor 3010 recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor 3045. Accordingly, the processor 3010 issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor 3045. Coprocessor(s) 3045 accept and execute the received coprocessor instructions.

Referring now to FIG. 31, shown is a block diagram of a first more specific exemplary system 3100 in accordance with an embodiment of the present invention. As shown in FIG. 31, multiprocessor system 3100 is a point-to-point interconnect system, and includes a first processor 3170 and a second processor 3180 coupled via a point-to-point interconnect 3150. Each of processors 3170 and 3180 may be some version of the processor 2900. In one embodiment of the invention, processors 3170 and 3180 are respectively processors 3010 and 3015, while coprocessor 3138 is coprocessor 3045. In another embodiment, processors 3170 and 3180 are respectively processor 3010 coprocessor 3045.

Processors 3170 and 3180 are shown including integrated memory controller (IMC) units 3172 and 3182, respectively. Processor 3170 also includes as part of its bus controller units point-to-point (P-P) interfaces 3176 and 3178; similarly, second processor 3180 includes P-P interfaces 3186 and 3188. Processors 3170, 3180 may exchange information via a point-to-point (P-P) interface 3150 using P-P interface circuits 3178, 3188. As shown in FIG. 31, IMCs 3172 and 3182 couple the processors to respective memories, namely a memory 3132 and a memory 3134, which may be portions of main memory locally attached to the respective processors.

Processors 3170, 3180 may each exchange information with a chipset 3190 via individual P-P interfaces 3152, 3154 using point to point interface circuits 3176, 3194, 3186, 3198. Chipset 3190 may optionally exchange information with the coprocessor 3138 via a high-performance interface 3192. In one embodiment, the coprocessor 3138 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

A shared cache (not shown) may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

Chipset 3190 may be coupled to a first bus 3116 via an interface 3196. In one embodiment, first bus 3116 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another I/O interconnect bus, although the scope of the present invention is not so limited.

As shown in FIG. 31, various I/O devices 3114 may be coupled to first bus 3116, along with a bus bridge 3118 which couples first bus 3116 to a second bus 3120. In one embodiment, one or more additional processor(s) 3115, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus 3116. In one embodiment, second bus 3120 may be a low pin count (LPC) bus. Various devices may be coupled to a second bus 3120 including, for example, a keyboard and/or mouse 3122, communication devices 3127 and a storage unit 3128 such as a disk drive or other mass storage device which may include instructions/code and data 3130, in one embodiment. Further, an audio I/O 3124 may be coupled to the second bus 3116. Note that other architectures are possible. For example, instead of the point-to-point architecture of FIG. 31, a system may implement a multi-drop bus or other such architecture.

Referring now to FIG. 32, shown is a block diagram of a second more specific exemplary system 3200 in accordance with an embodiment of the present invention. Like elements in FIGS. 31 and 32 bear like reference numerals, and certain aspects of FIG. 31 have been omitted from FIG. 32 in order to avoid obscuring other aspects of FIG. 32.

FIG. 32 illustrates that the processors 3170, 3180 may include integrated memory and I/O control logic (“CL”) 3272 and 3282, respectively. Thus, the CL 3272, 3282 include integrated memory controller units and include I/O control logic. FIG. 32 illustrates that not only are the memories 3132, 3134 coupled to the CL 3172, 3182, but also that I/O devices 3214 are also coupled to the control logic 3172, 3182. Legacy I/O devices 3215 are coupled to the chipset 3190.

Referring now to FIG. 33, shown is a block diagram of a SoC 3300 in accordance with an embodiment of the present invention. Similar elements in FIG. 29 bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. In FIG. 33, an interconnect unit(s) 3302 is coupled to: an application processor 3310 which includes a set of one or more cores 332A-N, cache units 2904A-N, and shared cache unit(s) 2906; a system agent unit 2910; a bus controller unit(s) 2916; an integrated memory controller unit(s) 2914; a set or one or more coprocessors 3320 which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit 3330; a direct memory access (DMA) unit 3332; and a display unit 3340 for coupling to one or more external displays. In one embodiment, the coprocessor(s) 3320 include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the invention may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Program code, such as code 3130 illustrated in FIG. 31, may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as, for example; a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

The program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.

One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.

Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritable's (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMS) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.

Accordingly, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.

Emulation (Including Binary Translation, Code Morphing, Etc.)

In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on processor, off processor, or part on and part off processor.

FIG. 34 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. FIG. 34 shows a program in a high level language 3402 may be compiled using an first compiler 3404 to generate a first binary code (e.g., x86) 3406 that may be natively executed by a processor with at least one first instruction set core 3416. In some embodiments, the processor with at least one first instruction set core 3416 represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The first compiler 3404 represents a compiler that is operable to generate binary code of the first instruction set 3406 (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one first instruction set core 3416. Similarly, FIG. 34 shows the program in the high level language 3402 may be compiled using an alternative instruction set compiler 3408 to generate alternative instruction set binary code 3410 that may be natively executed by a processor without at least one first instruction set core 3414 (e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif. and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, Calif.). The instruction converter 3412 is used to convert the first binary code 3406 into code that may be natively executed by the processor without an first instruction set core 3414. This converted code is not likely to be the same as the alternative instruction set binary code 3410 because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter 3412 represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have a first instruction set processor or core to execute the first binary code 3406. 

1. A processor comprising: decode circuitry to decode an instruction having fields to identify a first source matrix operand, a second source matrix operand, and a destination matrix pair operand; and execution circuitry to execute the decoded instruction to: compute a result by performing dot product operations on data elements from the identified first source matrix operand and the identified second source matrix operand, and accumulate the result into data element positions of the destination matrix pair operand, wherein data element positions of the destination matrix pair operand are larger than a size of the data elements of the identified first source matrix operand and the identified second source matrix operand.
 2. The processor of claim 1, wherein the data elements from the identified first source matrix operand and the identified second source matrix operand are signed doubleword elements, and wherein the data elements from the identified destination matrix operand are quadwords.
 3. The processor of claim 1, wherein the execution circuitry comprises a plurality of fused-multiply adders.
 4. The processor of claim 1, wherein the identified destination matrix pair operand comprises a pair of groups of packed data registers.
 5. The processor of claim 4, wherein a first group of the pair of groups of packed data registers is to store a first half of consecutive columns of a matrix and a second group of the pair of groups of packed data registers is to store a first half of consecutive columns of the matrix.
 6. The processor of claim 4, wherein a first group of the pair of groups of packed data registers is to store a first half of consecutive rows of a matrix and a second group of the pair of groups of packed data registers is to store a first half of consecutive rows of the matrix.
 7. The processor of claim 4, wherein a first group of the pair of groups of packed data registers is to store a first half of interleaved columns of a matrix and a second group of the pair of groups of packed data registers is to store a first half of interleaved columns of the matrix.
 8. The processor of claim 4, wherein a first group of the pair of groups of packed data registers is to store a first half of interleaved rows of a matrix and a second group of the pair of groups of packed data registers is to store a first half of interleaved rows of the matrix.
 9. The processor of claim 1, wherein a fault is generated when a number of rows of the identified destination matrix pair operand is different than a number of rows of the identified first source matrix operand.
 10. The processor of claim 1, wherein a fault is generated when a number of columns of the identified destination matrix pair operand is different than a number of columns of the identified second source matrix operand.
 11. The processor of claim 1, wherein the execution circuitry is further to zero data element positions that do not have an accumulate value.
 12. A method comprising: decoding an instruction having fields to identify a first source matrix operand, a second source matrix operand, and a destination matrix pair operand; and executing the decoded instruction to: compute a result by performing dot product operations on data elements from the identified first source matrix operand and the identified second source matrix operand, and accumulate the result into data element positions of the destination matrix pair operand, wherein data element positions of the destination matrix pair operand are larger than a size of the data elements of the identified first source matrix operand and the identified second source matrix operand.
 13. The method of claim 12, wherein the data elements of the identified first source matrix operand and the identified second source matrix operand are signed doubleword elements, and wherein the data elements of the identified destination matrix operand are quadwords.
 14. The method of claim 12, wherein the executing uses a plurality of fused-multiply adders.
 15. The method of claim 12, wherein the identified destination matrix pair operand comprises a pair of groups of packed data registers.
 16. The method of claim 15, wherein a first group of the pair of groups of packed data registers is to store a first half of consecutive columns of a matrix and a second group of the pair of groups of packed data registers is to store a first half of consecutive columns of the matrix.
 17. The method of claim 15, wherein a first group of the pair of groups of packed data registers is to store a first half of consecutive rows of a matrix and a second group of the pair of groups of packed data registers is to store a first half of consecutive rows of the matrix.
 18. The method of claim 15, wherein a first group of the pair of groups of packed data registers is to store a first half of interleaved columns of a matrix and a second group of the pair of groups of packed data registers is to store a first half of interleaved columns of the matrix.
 19. The method of claim 15, wherein a first group of the pair of groups of packed data registers is to store a first half of interleaved rows of a matrix and a second group of the pair of groups of packed data registers is to store a first half of interleaved rows of the matrix.
 20. The method of claim 12, wherein a fault is generated when a number of rows of the identified destination matrix pair operand is different than a number of rows of the identified first source matrix operand. 21-25. (canceled) 